1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a thin film transistor in which a stable silicide layer is formed apart from a channel region.
2. Description of Related Art
The technique for forming as a switching element a thin film transistor (TFT) formed of silicon on a transparent insulating substrate such as a glass substrate is widely used in an active matrix type of liquid crystal device (LCD). Further, research and development of an LCD having high performance such as a large size high resolution LCD have proceeded flourishingly.
As one method for realizing such a high performance TFT is known a method disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heise13-4566) in which the load of position aligning in a photo-lithography process is eliminated by use of self-alignment technique so that a channel length of the TFT can be shortened and a parasitic capacitance can be reduced. FIGS. 1A to 1F are cross sectional views of a TFT in the processes of a first conventional manufacturing method of the TFT.
First, as shown in FIG. 1A, a gate electrode 102 of a chromium (Cr) film is selectively formed on a glass substrate 101 and then a gate insulating film 103 of an amorphous silicon nitride film (to be referred to as "a-SiN film" hereinafter) is formed on the surface of the substrate including the gate electrode 102. On the gate insulating film 103 by plasma CVD method are sequentially laminated an i-type semiconductor film (to be referred to as "i-layer" hereinafter) 104 of an i-type amorphous silicon film (to be referred to as "a-Si film" hereinafter), a protection insulating film or a channel passivation film 105a of the a-SiN film having a low etching rate, and a protection insulating film 105b of the a-SiN film having an etching rate greater than that of the protection insulating film l05a. In this case, the thickness of the lower protection insulating film 105a is smaller than a projected range of impurity ions in an ion implantation process to be executed later. On the other hand, the film thickness of the upper protection insulating film 105b is sufficiently greater than the projected range of impurity ions. Subsequently, a positive type of photoresist film 106 is spin-coated on the protection insulating film 105b.
Next, as shown in FIG. 1B, the photoresist film 106 is exposed by light from the rear side of the glass substrate 101 using the gate electrode 102 as a photo-mask and then patterned in self-alignment with the gate electrode 102.
Next, as shown in FIG. 1C, the proteation insulating films 105b and 105a are sequentially dry-etched and patterned using the patterned photoresist film 106 as a mask.
Next, as shown in FIG. 1D, the patterned protection insulating films 105a and 105b are wet-etched in the state in which the patterned photoresist film 106 is remained using the difference between the protection insulating films 105a and 105b in etching rate such that the width of the upper protection insulating film 105b is smaller than that of the lower protection insulating film 105a.
Next, as shown in FIG. 1E, after the patterned photoresist film 106 is removed, phosphorus ions 110 are injected in the i-layer 104 by an ion implantation method using the protection insulating films 105a and 105b as a mask. As a result, an n.sup.+ -layer 111 is formed as source and drain regions in the i-layer 104. In this case, the source and drain regions extend to portions of the i-layer 104 below a part of the lower protection insulating film 105a exposed by removing or etching the upper protection insulating film 105b.
Next, as shown in FIG. 1F, a chromium (Cr) film is formed on the n.sup.+ -layer 111 by a sputtering method immediately after a natural oxide film formed on the n'-layer 111 is removed by diluted hydrofluoric acid solution. At this time, a Cr silicide layer 108 is formed at an interface using reaction between the Cr film and the n'-layer 111, ie., mutual diffusion. Subsequently, a part of the non-reaction Cr film is selectively etched so that source and drain electrodes are constituted of the remained Cr film 109 and the silicide layers 108.
As seen from the above description, the Cr silicide layer 108 is formed in the form buried in the n.sup.+ -layer 111. Therefore, there can be suppressed the degradation of hole blocking characteristic which degradation is caused by direct contact between the Cr silicide layer 108 and the channel region of the i-layer 104.
However, in this conventional example, since the dry etching of the protection insulating films 105a and 105b is anisotropic, the protection insulating films 105a and 105b are not etched so much so that the silicide layer directly contacts with the channel region. Further, a large amount of defects such as dangling bonds are also generated on the i-layer 104 surface after the ion implantation, i.e., the n.sup.+ layer 111 surface. As a result, the natural oxide film is formed on the surface in atmosphere with a very short time. The natural oxide film acts as a barrier layer which suppresses the reaction between the n'-layer 111 and the Cr film, so that the Cr silicide layer 108 is not entirely formed or formed to have resistivity. This results in remarkable reduction of the ON current of the TFT. Therefore, before the formation of the Cr film, it is essentially necessary to stabilize the i-layer surface by hydrogen atoms at the same time when the natural, oxide film is removed by the diluted hydrofluoric acid solution.
Even in this method, however, a new natural oxide film is formed with a short time after the hydrofluoric acid treatment because a very large amount of defects are present on the n.sup.+ -layer 111. Thus, the constraint that the Cr film must be formed speedily after the hydrofluoric acid treatment is remained in the manufacturing process. Further, the protection insulating films 105a and 105b having used as a mask in the ion implantation are damaged through the ion implantation to be readily etched. Accordingly, the width of the protection insulating films 105a and 105b is decreased narrower than the width between the n.sup.+ -layers 111, i.e., the channel region on the hydrofluoric acid treatment. As a result, the Cr silicide layers 108 formed in the subsequent process directly contact the channel region of the i-layer 104. This problem is often caused. This problem results in remarkable increase of the OFF current of the TFT so that the ratio of the ON and OFF currents of the TFT as a switching element is made small. In addition, there is another problem in that it is not allowed in the manufacturing process to make the i-layer 104 thin because the dry etching process patterning the protection insulating films 105a and 105b is interposed in the manufacturing process, so that over-etching of the lower i-layer 104 cannot be avoided.
The above problems cause degradation of reproducibility and reliability of the manufacturing process, and further degradation of a process margin. Therefore, another manufacturing process is needed to provide the TFT stably.
The other manufacturing process is disclosed in Japanese Laid Open Patent Disclosure (Jp-A-Heise5-211166), which improves the first conventional method. FIGS. 2A to 2E are cross sectional views of a TFT in the processes of a second conventional manufacturing method of the TFT.
First, as shown in FIG. 2A, a gate electrode 202 of a chromium (Cr) film is selectively formed on a glass substrate 201 and then a gate insulating film 203, the i-layer 204, and a first protection insulating film 214 having a high etching rate to hydrofluoric acid are sequentially laminated on the surface of the glass substrate 201 including the gate electrode 202 by a plasma CVD method. In this case, the first protection insulating film 214 has the film thickness sufficiently greater than the projected range of impurity ions in an ion implantation to be executed later. Next, a positive type of photoresist film 206 is spin-coated on the first protection insulating film 214. Subsequently, the photoresist film 206 is exposed by light from the rear side of the glass substrate 201 using the gate electrode 102 as a photo-mask and then patterned in self-alignment with the gate electrode 202. In this case, the rear exposure time and development time are adjusted in such a manner that the pattern width of the photoresist film 206 is made narrower than that of the gate electrode 202.
Next, as shown in FIG. 2B, the first protection insulating films 214 is dry-etched and patterned using the patterned photoresist film 206 as a mask.
Next, as shown in FIG. 2C, after the patterned photoresist film 206 is removed, phosphorus ions 210 are injected in the i-layer 204 by an ion implantation method using the first protection insulating film 214 as a mask. As a result, n.sup.+ -layers 111 are formed as source and drain regions.
Next, as shown in FIG. 2D, after the first protection insulating film 214 used as a mask in the ion implantation is quickly removed by hydrofluoric acid solution, a second protection insulating film 215 having low etching rate to hydrofluoric acid is formed on the surface including the n.sup.+ -layer 211 by using the plasma CVD method again. Then, a positive type of photoresist film 216 is spin-coated on the second protection insulating film 215, exposed from the rear side of the glass substrate 201 using the gate electrode 202 as a mask, and patterned in self-alignment with the gate electrode 202. In this process, the rear exposure time and development time are adjusted in such a manner that the pattern width of the photoresist film 216 is approximately equal to that of the gate electrode 202. Subsequently, the second protection insulating film 215 is patterned by a dry etching process using the patterned photoresist film 216 as a mask.
Next, as shown in FIG. 2E, after the photoresist film 216 is removed, a natural oxide film formed on the n.sup.+ -layer 211 is removed by diluted hydrofluoric acid solution. Thereafter, a Cr film is immediately formed by a sputtering method, so that a Cr silicide film 208 is formed at the interface between the n.sup.+ -layer 211 and the Cr film by use of the reaction of the n.sup.+ -layer 211 and the Cr film, Subsequently, a part of the non-reaction Cr film is selectively etched so that source and drain electrodes 209 composed of Cr film and the silicide layer are formed.
In the above second conventional method, two protection insulating films, i.e., the first protection insulating film 214 used in the ion implantation and the second protection insulating film 215 used in the formation of the Cr silicide layer 208 are separately and independently used. The n.sup.+ -layer 211 and the Cr silicide layer 208 are formed such that they are separated from each other, using the difference between the protection insulating films 214 and 215 in pattern width, Therefore, the problems in the first conventional manufacturing method are partially solved.
However, in the second conventional manufacturing method, there is a problem in that two processes for forming the protection insulating films 214 and 215 and two rear exposure processes for patterning are required so that the number of processes is increased. Further, since the pattern width of the first protection insulating film 214 is required to be narrow, the process margin is small. Therefore, it is difficult to apply this method to a method of manufacturing a TFT having a channel length shorter than 4 .mu.m. In addition, since it is necessary that after the first protection insulating film 215 is once removed, the second protection insulating film 215 is newly formed, the i-layer 204 surface as an interface surface between the i-layer 204 and the protection insulating film 214 or 215 is exposed in the atmosphere or plasma during the formation of the insulating film. For this reason, the interface characteristic is degraded easily, resulting in degradation of TFT characteristics. Furthermore, when the Cr silicide layer 208 is formed after the ion implantation and dry etching, there is another problem in that it is difficult to always form the Cr silicide layer 208 having a low resistivity in a good state, because a natural oxide film is very quickly formed on the Cr silicide film 208. Also, since the patterning processes of the protection insulating films 214 and 215 by dry etching are necessary, there is still remained the problem in that the i-layer 204 cannot be made thin.